Main Program

Main Menu

Authors & Reviewers

Programs

Participants

Main Program

Highlights

Tutorials and Workshops are scheduled on Saturday and Sunday.

Sunday June 10
18:00 – 20:00		Welcome Reception
Monday June 11
8:15 - 8:45		Breakfast
8:45 - 9:00		Opening Remarks: Shih-Lien Lu and Josep Torrellas
9:00 - 10:00		Keynote I: New Insights from Neuroscience and the Future of Intelligent Machines Jeff Hawkins, Founder, Numenta [abstract] [slides]
10:00 - 10:30		Coffee Break
10:30 - 12:10		Session 1: Memory Systems (I)
12:10 - 13:40		Conference Luncheon
13:40 - 15:20		Session 2A: GPU Architectures	Session 2B: Architectures for Security
15:20 - 15:50		Snack Break
15:50 - 17:30	15:50 - 16:40	Session 3A: Interconnection Networks	Session 3B-1: Architectures for Software Productivity
	16:40 - 17:30		Session 3B-2: Heterogeneity
18:00 – 20:00		Business Meeting
Tuesday June 12
8:00 - 8:30		Breakfast
8:30 - 9:30		Keynote II: Extreme Scale Computing Justin Rattner, Chief Technology Officer, Intel [abstract] [slides]
9:40 - 10:30		Session 4: Circuits and Technology
10:30 - 11:00		Coffee Break
11:00 - 12:15		Session 5: Reliability
12:15 - 14:15		Awards Luncheon
14:15 - 15:30		Session 6A: Cache Systems	Session 6B: Dependable Architectures
15:30 - 16:00		Snack Break
16:00 - 17:15		Session 7A: Memory Systems (II)	Session 7B: Scheduling and Resource Management
17:30 – 20:00		Excursion / Banquet at Oregon Museum of Science and Industry
Wednesday June 13
8:00 - 8:30		Breakfast
8:30 - 9:20		Session 8: Application Analysis
9:25 - 10:15		Session 9: Virtualized Systems
10:15 - 10:45		Coffee Break
10:45 - 12:00		Session 10A: Data Centers	Session 10B: HW/SW Interface and Flexibility
12:00 - 12:10		Adjourn
13:00 - 18:00		Excursion to Mount Hood / Timberline Lodge

Detailed Program

Sunday June 10
18:00 – 20:00	Welcome Reception
Monday June 11
8:15 - 8:45	Breakfast
8:45 - 9:00	Opening Remarks: Shih-Lien Lu and Josep Torrellas
9:00 - 10:00	Keynote I: New Insights from Neuroscience and the Future of Intelligent Machines Jeff Hawkins, Founder, Numenta [abstract] [slides] Chair: Shih-Lien Lu, Intel
10:00 - 10:30	Coffee Break
10:30 - 12:10	Session 1: Memory Systems (I) Chair: Per Stenstrom, Chalmers University of Technology
10:30 - 12:10	RAIDR: Retention-Aware Intelligent DRAM Refresh Jamie Liu, Ben Jaiyen, Richard M. Veras, and Onur Mutlu (Carnegie Mellon University) PARDIS: A Programmable Memory Controller for the DDRx Interfacing Standards Mahdi Nazm Bojnordi and Engin Ipek (University of Rochester) BOOM: Enabling Mobile Memory Based Low-Power Server DIMMs Doe Hyun Yoon, Jichuan Chang, Naveen Muralimanohar, and Parthasarathy Ranganathan (HP Labs) Towards Energy-Proportional Datacenter Memory with Mobile DRAM Krishna T. Malladi, Frank Austin Nothaft, and Karthika Periyathambi (Stanford University), Benjamin C Lee (Duke University), and Christos Kozyrakis and Mark Horowitz (Stanford University)
12:10 - 13:40	Conference Luncheon
13:40 - 15:20	Session 2A: GPU Architectures Chair: Doug Carmean, Intel
	Simultaneous Branch and Warp Interweaving for Sustained GPU Performance Nicolas Brunie (Kalray and ENS de Lyon), Sylvain Collange (Universidade Federal de Minas Gerais), and Gregory Diamos (NVIDIA Research) CAPRI: Prediction of Compaction-Adequacy for Handling Control-Divergence in GPGPU Architectures Minsoo Rhu and Mattan Erez (The University of Texas at Austin) iGPU: Exception Support and Speculative Execution on GPUs Jaikrishnan Menon, Marc de Kruijf, and Karthikeyan Sankaralingam (University of Wisconsin, Madison) Boosting Mobile GPU Performance With A Decoupled Access/Execute Fragment Processor Jose Maria Arnau and Joan Manuel Parcerisa (Technical University of Catalonia) and Polychronis Xekalakis (Intel Labs Barcelona)
	Session 2B: Architectures for Security Chair: Ruby Lee, Princeton University
	Branch Regulation: Low-Overhead Protection from Code Reuse Attacks Mehmet Kayaalp, Meltem Ozsoy, Nael Abu-Ghazaleh, and Dmitry Ponomarev (SUNY at Binghamton) Side-Channel Vulnerability Factor: A Metric for Measuring Information Leakage John Demme, Robert Martin, Adam Waksman, and Simha Sethumadhavan (Columbia University) Time Warp: Rethinking Timekeeping and Performance Measurement Mechanisms to Mitigate Side Channels Robert Martin, John Demme, and Simha Sethumadhavan (Columbia University) Inspection Resistant Memory: Architectural Support for Security from Physical Examination Jonathan Valamehr and Timothy Sherwood (UC Santa Barbara), Andrew Putnam, Daniel Shumow, Melissa Chase, and Seny Kamara (Microsoft Research), and Vinod Vaikuntanathan (University of Toronto)
15:20 - 15:50	Snack Break
15:50 - 17:30	Session 3A: Interconnection Networks Chair: John Carter, IBM
	Tolerating Process Variations in Nanophotonic On-chip Networks Yi Xu, Jun Yang, and Rami Melhem (University of Pittsburgh) A Micro-architectural Analysis of Switched Photonic Multi-chip Interconnects Pranay Koka, Michael O. McCracken, and Herb Schwetman (Oracle Labs), Chia-Hsin Chen (MIT), and Xuezhe Zheng, Ron Ho, Kannan Raj, and Ashok V. Krishnamoorthy (Oracle Labs) Enhancing Effective Throughput for Transmission Line-Based Bus Aaron Carpenter, Jianyun Hu, Ovunc Kocabas, Michael Huang, and Hui Wu (University of Rochester) A Case for Random Shortcut Topologies for HPC Interconnects Michihiro Koibuchi (National Institute of Informatics), Hiroki Matsutani and Hideharu Amano (Keio University), D. Frank Hsu (Fordham University), and Henri Casanova (University of Hawaii at Manoa)
	Session 3B-1 (15:50 - 16:40): Architectures for Software Productivity Chair: David Kaeli, Northeastern University
	Watchdog: Hardware for Safe and Secure Manual Memory Management and Full Memory Safety Santosh Nagarakatte, Milo M K Martin, and Steve Zdancewic (University of Pennsylvania) RADISH: Always-On Sound and Complete Race Detection in Software and Hardware Joseph Devietti and Benjamin Wood (University of Washington), Karin Strauss (Microsoft Research and University of Washington), Luis Ceze and Dan Grossman (University of Washington), and Shaz Qadeer (Microsoft Research)
	Session 3B-2 (16:40 - 17:30): Heterogeneity Chair: Antonio Gonzalez, Intel and UPC
	Scheduling Heterogeneous Multi-Cores through Performance Impact Estimation (PIE) Kenzo Van Craeynest (Ghent University), Aamer Jaleel (Intel), Lieven Eeckhout (Ghent University), and Paolo Narvaez and Joel Emer (Intel/MIT) The Yin and Yang of Power and Performance for Asymmetric Hardware and Managed Software Ting Cao, Stephen M Blackburn and Tiejun Gao (the Australian National University) and Kathryn S McKinley (Microsoft Research, the University of Texas at Austin)
18:00 – 20:00	Business Meeting
Tuesday June 12
8:00 - 8:30	Breakfast
8:30 - 9:30	Keynote II: Extreme Scale Computing Justin Rattner, Chief Technology Officer, Intel [abstract] [slides] Chair: Josep Torrellas, University of Illinois
9:40 - 10:30	Session 4: Circuits and Technology Chair: Trevor Mudge, University of Michigan
9:40 - 10:30	Lane Decoupling for Improving the Timing-Error Resiliency of Wide-SIMD Architectures Evgeni Krimer (The University of Texas at Austin), Patrick Chiang (Oregon State University), and Mattan Erez (The University of Texas at Austin) VRSync: Characterizing and Eliminating Synchronization-Induced Voltage Emergencies in Many-core Processors Timothy N. Miller, Renji Thomas, Xiang Pan, and Radu Teodorescu (The Ohio State University)
10:30 - 11:00	Coffee Break
11:00 - 12:15	Session 5: Reliability Chair: Pradip Bose, IBM
11:00 - 12:15	Euripus: A Flexible Unified Hardware Memory Checkpointing Accelerator for Bidirectional Debugging and Reliability Ioannis Doudalis (Intel, Georgia Institute of Technology) and Milos Prvulovic (Georgia Institute of Technology) A First-Order Mechanistic Model for Architectural Vulnerability Factor Arun Arvind Nair (University of Texas at Austin), Stijn Eyerman and Lieven Eeckhout (Ghent University, Belgium), and Lizy Kurian John (University of Texas at Austin) LOT-ECC: LOcalized and Tiered Reliability Mechanisms for Commodity Memory Systems Aniruddha N. Udipi (University of Utah), Naveen Muralimanohar (HP Labs), Rajeev Balasubramonian and Al Davis (University of Utah), and Norman P. Jouppi (HP Labs)
12:15 - 14:15	Awards Luncheon
14:15 - 15:30	Session 6A: Cache Systems Chair: Jose Martinez, Cornell University
	Reducing memory reference energy with Opportunistic Virtual Caching Arkaprava Basu, Michael M. Swift, and Mark D. Hill (University of Wisconsin-Madison) Improving Writeback Efficiency with Decoupled Last-Write Prediction Zhe Wang, Samira M. Khan, and Daniel A. Jiménez (The University of Texas at San Antonio) FLEXclusion: Balancing Cache Capacity and On-Chip Traffic via Flexible Exclusion Jaewoong Sim (Georgia Institute of Technology), Jaekyu Lee (Georgia Institute of Technology), Moinuddin K. Qureshi (Georgia Institute of Technology), and Hyesoon Kim (Georgia Institute of Technolog)
	Session 6B: Dependable Architectures Chair: Kunle Olukotun, Stanford University
	Setting an Error Detection Infrastructure with Low Cost Acoustic Wave Detectors Gaurang Upasani (UPC), Xavier Vera (Intel), and Antonio Gonzalez (Intel & UPC) Viper: Virtual Pipelines for Enhanced Reliability Andrea Pellegrini, Joseph Greathouse and Valeria Bertacco (University of Michigan) A Defect-Tolerant Accelerator for Emerging High-Performance Applications Olivier Temam (INRIA)
15:30 - 16:00	Snack Break
16:00 - 17:15	Session 7A: Memory Systems (II) Chair: Babak Falsafi, EPFL
	A Case for Exploiting Subarray-Level Parallelism (SALP) in DRAM Yoongu Kim, Vivek Seshadri, Donghyuk Lee, Jamie Liu, and Onur Mutlu (Carnegie Mellon University) PreSET: Improving Read-Write Performance of Phase Change Memories by Exploiting Asymmetry in Write Times Moinuddin Qureshi (GT) and Michele Franceschini, Ashish Jagmohan, and Luis Lastras (IBM) Buffer-On-Board Memory System Elliott Cooper-Balis, Paul Rosenfeld, and Bruce Jacob (University Of Maryland)
	Session 7B: Scheduling and Resource Management Chair: Mattan Erez, University of Texas, Austin
	PAQ: Physically Addressed Queuing for Resource Conflict Avoidance in Solid State Disk Myoungsoo Jung, Ellis H. Wilson III, and Mahmut Kandemir (The Pennsylvania State University) Staged Memory Scheduling: Achieving High Performance and Scalability in Heterogeneous Systems Rachata Ausavarungnirun (Carnegie Mellon University), Gabriel Loh (Advanced Micro Devices), and Kevin Chang, Lavanya Subramanian, and Onur Mutlu (Carnegie Mellon University) Probabilistic Shared Cache Management(PriSM) R Manikantan (Indian Institute of Science), Kaushik Rajan (Microsoft Research), and R Govindarajan (Indian Institute of Science)
17:30 – 20:00	Excursion / Banquet at Oregon Museum of Science and Industry
Wednesday June 13
8:00 - 8:30	Breakfast
8:30 - 9:20	Session 8: Application Analysis Chair: Alaa Alameldeen, Intel
8:30 - 9:20	Can Traditional Programming Bridge the Ninja Performance Gap for Parallel Computing Applications? Nadathur Satish, Changkyu Kim, Jatin Chhugani, Hideki Saito, Rakesh Krishnaiyer, Mikhail Smelyanskiy, Milind Girkar, and Pradeep Dubey (Intel Corporation) Harmony: Collection and Analysis of Parallel Block Vectors Melanie Kambadur, Kui Tang, and Martha Kim (Columbia University)
9:25 - 10:15	Session 9: Virtualized Systems Chair: Mark Hill, University of Wisconsin
9:25 - 10:15	Configurable Fine-Grain Protection for Multicore Processor Virtualization David Wentzlaff (Princeton University), Christopher J. Jackson (Tilera), Patrick Griffin (Google), and Anant Agarwal (Tilera) Revisiting Hardware-Assisted Page Walks for Virtualized Systems Jeongseob Ahn, Seongwook Jin, and Jaehyuk Huh (KAIST)
10:15 - 10:45	Coffee Break
10:45 - 12:00	Session 10A: Data Centers Chair: James Tuck, North Carolina State University
	Managing Distributed UPS Energy for Effective Power Capping in Data Centers Vasileios Kontorinis, Liuyi Zhang, Baris Aksanli, Jack Sampson, and Houman Homayoun (UCSD), Eddie Pettis (Google), and Tajana Rosing and Dean Tullsen (UCSD) Scale-Out Processors Pejman Lotfi-Kamran and Boris Grot (EPFL), Michael Ferdman (CMU/EPFL), Stavros Volos, Onur Kocberber, Javier Picorel, Almutaz Adileh, and Djordje Jevdjic (EPFL), Sachin Idgunji and Emre Ozer (ARM), and Babak Falsafi (EPFL) iSwitch: Coordinating and Optimizing Renewable Energy Powered Server Clusters Chao Li, Amer Qouneh, and Tao Li (University of Florida)
	Session 10B: HW/SW Interface and Flexibility Chair: Kim Hazelwood, University of Virginia and Google
	End-To-End Sequential Consistency Abhayendra Singh (University of Michigan, Ann Arbor), Satish Narayanasamy (University of Michigan, Ann Arbor), Daniel Marino (Symantec), Todd Millstein (University of California, Los Angeles), and Madanlal Musuvathi (Microsoft Research, Redmond) BlockChop: Dynamic Squash Elimination for Hybrid Processor Architecture Jason Mars (University of Virginia) and Naveen Kumar (Intel Labs) The Dynamic Granularity Memory System Doe Hyun Yoon (HP Labs) and Michael Sullivan, Min Kyu Jeong, and Mattan Erez (UT Austin)
12:00 - 12:10	Adjourn
13:00 - 18:00	Excursion to Mount Hood / Timberline Lodge